Thin film magnetic memory device provided with program element

ABSTRACT

A program element has a magnetic layer electrically connected between first and second nodes. At least a portion of the magnetic layer forms a link portion designed to be blown with external-laser irradiation. The magnetic layer is provided in the same layer as and with the same structure as a tunneling magneto-resistance element in an MTJ memory cell. An electrical contact between the magnetic layer and respective one of the first and second nodes has the same structure as the electrical contact between the tunneling magneto-resistance element and an interconnection provided in the same metal interconnection layer as respective one of the first and second nodes in the MTJ memory cell.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to thin film magnetic memory devices, andmore particularly to a thin film magnetic memory device provided with amemory cell having a magnetic tunnel junction and a program element forstoring information in a fixed manner.

2. Description of the Background Art

A magnetic random access memory device (MRAM device) has attractedattention as a memory device capable of non-volatile data storage withlow power consumption. The MRAM device stores data in a non-volatilemanner using a plurality of thin film magnetic elements formed on asemiconductor integrated circuit, and permits random access to therespective thin film magnetic element.

In particular, it has been reported that provision of memory cells(hereinafter, also referred to as “MTJ memory cells”) formed of thinfilm magnetic elements utilizing magnetic tunnel junctions (MTJ)significantly improves the performance of the MRAM device. The MTJmemory cell stores data as it is magnetized, by a magnetic fieldgenerated by a data write current, in a direction corresponding to datato be written. Such an MRAM device is disclosed, e.g., in “A 10 ns Readand Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction andFET Switch in each Cell”, 2000 IEEE ISSCC Digest of Technical Papers,TA7.2.

A memory device is generally provided with a program element, such as afuse element, for the purposes of fixedly storing information necessaryfor redundancy repair, tuning information of an internal voltage andothers. In the MRAM device capable of storing data in each memory cellin a non-volatile manner, it is possible to use an excessive MTJ memorycell to constitute such a program element.

Alternatively, Japanese Patent Laying-Open No. 2002-117684 discloses,focusing on an insulating film forming a magnetic tunnel junction, aconfiguration for programming information in a fixed manner by causingbreakdown of the insulating film.

In the case of forming the program element with an excessive MTJ memorycell, however, data stored in the MTJ memory cell may be lost duringheat treatment after completion of a wafer process, through burn-in andpackaging steps, before shipment.

As a program element permitting more stable storage of information, afuse element which can be blown with laser irradiation in a wafer stateis known. The MRAM device, compared to a normal memory device, requiresadditional depositing and processing steps dedicated to formation of theMTJ memory cells. Thus, the number of other steps should be made assmall as possible. As such, it is desirable that formation of such afuse element does not require dedicated manufacturing steps.

Furthermore, the memory device is tested in each of wafer state,packaged state, and others. As such, there is a demand for a programelement which can program information accumulatively based on results ofthe plurality of tests.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a program element whichcan be fabricated in parallel with an MTJ memory cell in a manufacturingstep of the MTJ memory cell, without a need of a dedicated manufacturingstep, and a thin film magnetic memory device provided with a programcircuit which can program information accumulatively over a plurality ofsteps using the relevant program element.

A thin film magnetic memory device according to the present inventionincludes a plurality of magnetic memory cells permitting randomaccesses, and a program element storing information in a fixed manner.Each of the magnetic memory cells includes a conductive magnetic filmformed of a plurality of layers. The program element includes a linkportion which is electrically connected between first and second nodesand fusible by an external input. The link portion is formed of the samelayer as at least one of the plurality of layers constituting theconductive magnetic film.

Accordingly, a main advantage of the present invention is that, in thethin film magnetic memory device, the program element formed as a fuseelement utilizing the same structural portion as at least a portion ofthe conductive magnetic film constituting the magnetic memory cell (MTJmemory cell) can be manufactured in parallel with the magnetic memorycells in a manufacturing step of the magnetic memory cells withoutprovision of a manufacturing step dedicated to the program element. As aresult, a stable program element can be built in the thin film magneticmemory device, without an increase of the number of manufacturing stepsor the manufacturing cost.

A thin film magnetic memory device according to another configuration ofthe present invention includes a plurality of magnetic memory cellspermitting random accesses, and a program circuit storing information ina fixed manner. Each of the magnetic memory cells includes a tunnelingmagneto-resistance element which is formed of a plurality of layersincluding a conductive magnetic film and an insulating film and of whichresistance changes in accordance with magnetically written data. Theprogram circuit includes a first program element connected between firstand second nodes and formed of the plurality of layers as with thetunneling magneto-resistance element, an amplifier portion reading theinformation in accordance with a resistance between the first and secondnodes, and a first breakdown voltage apply portion applying a firstvoltage stress capable of causing breakdown of the insulating film inthe plurality of layers constituting the first program element betweenthe first and second nodes as appropriate. An upper layer side and alower layer side of the plurality of layers constituting the firstprogram element are electrically connected to one and the other of thefirst and second nodes. The first program element is shaped such that atleast a portion of the portion electrically connected between the firstand second nodes is fusible with a first external input.

With such a thin film magnetic memory device, the program circuit usingthe program element which can be fabricated without increasing thenumber of manufacturing steps is capable of programming informationbefore and after a packaging step independently from each other. Thatis, after information based on the operation test result in a waferstate, following completion of a wafer process, is programmed by laserirradiation, information obtained after the relevant step can beprogrammed by an external voltage input accompanied by breakdown. As aresult, defects detected, e.g., in a wafer test, a test after burn-inand a test after packaging, can be programmed accumulatively for repair.

A thin film magnetic memory device according to yet anotherconfiguration of the present invention includes a plurality of magneticmemory cells permitting random accesses, and a program circuit storinginformation in a fixed manner. Each of the plurality of magnetic memorycells includes a tunneling magneto-resistance element formed of aplurality of layers including a conductive magnetic film and aninsulating film and having a resistance changed in accordance withmagnetically written data. The program circuit includes a first programelement formed of the plurality of layers as with the tunnelingmagneto-resistance element, a first program interconnection electricallyconnected to the first program element and a first node, a first currentdriving portion for supplying the first program interconnection with acurrent for magnetically writing data to the first program element, andan amplifier portion reading the information in accordance with aresistance between the first and second nodes. An upper layer side and alower layer side of the plurality of layers constituting the firstprogram element are electrically connected to one and the other of thefirst program interconnection and the second node. The first programinterconnection is shaped such that at least a portion of its portionelectrically connected between the first program element and the firstnode is fusible by a first external input.

With such a thin film magnetic memory device, the program circuit usingthe program element which can be fabricated without increasing thenumber of manufacturing steps is capable of programming informationbefore and after blowing with laser irradiation independently from eachother. Thus, after information based on an operation test result in awafer test is programmed by magnetic writing, a test as to whether adesired operation is performed by the relevant information program canbe carried out without actual laser blowing. Further, the confirmedprogram information can be stored stably with laser blowing.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram showing an entire configuration ofan MRAM device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of the memory arrayshown in FIG. 1.

FIG. 3 is a conceptual diagram illustrating a configuration and datastorage principle of an MTJ memory cell.

FIG. 4 is a conceptual diagram illustrating a relation between a datawrite current of the MTJ memory cell and a magnetization direction of atunneling magneto-resistance element.

FIG. 5 is a cross sectional view showing a structure of the MTJ memorycell.

FIG. 6 is a cross sectional view showing by way of example a structureof the tunneling magnetic layer.

FIG. 7 shows operational waveforms during a data read operation and adata write operation, for illustrating replacement/repair in the MRAMdevice shown in FIGS. 1 and 2.

FIG. 8 is a circuit diagram showing a configuration of a redundancycontrol unit as an application example of the program element accordingto the first embodiment.

FIGS. 9A-9C show first structure examples of the program elementaccording to the first embodiment.

FIGS. 10A-10C show second structure examples of the program elementaccording to the first embodiment.

FIGS. 11A-11C show third structure examples of the program elementaccording to the first embodiment.

FIG. 12 is a circuit diagram showing a configuration of a redundancycontrol unit according to a second embodiment of the present invention.

FIG. 13 is a circuit diagram showing a configuration of a programcircuit according to the second embodiment.

FIG. 14 shows arrangement of the program elements in the program circuitshown in FIG. 13.

FIG. 15 is a flowchart illustrating a time period for application of aprogram input to the program circuit according to the second embodiment.

FIG. 16 shows by way of example a structure of the program elementaccording to a third embodiment of the present invention.

FIG. 17 is a conceptual diagram illustrating arrangement of a programword line and a program bit line with respect to the program cellaccording to the third embodiment.

FIG. 18 is a circuit diagram showing a current supplying configurationat the time of data write to program cells.

FIG. 19 is a circuit diagram showing a configuration of the programcircuit according to the third embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described indetail with reference to the drawings.

First Embodiment

Referring to FIG. 1, the MRAM device 1 according to the first embodimentof the present invention performs random access in accordance withexternally supplied control signal CMD and address signal ADD, andperforms input of write data DIN and output of read data DOUT. The dataread operation and the data write operation in MRAM device 1 areperformed at timings in synchronization with an externally applied clocksignal CLK, for example. Alternatively, the operating timings may bedetermined within the device, unprovided with external clock signal CLK.

MRAM device 1 includes: an address terminal 2 receiving input of addresssignal ADD; a control signal terminal 3 receiving input of controlsignal CMD and clock signal CLK; a signal terminal 4 a receiving inputof a control signal PRG that is activated in a program operation; acontrol circuit 5 for controlling the entire operations of MRAM device 1in response to control signal CMD and clock signal CLK; and a memoryarray 10 having a plurality of MTJ memory cells arranged in rows andcolumns.

Memory array 10, whose configuration will be described later in detail,includes: a plurality of normal MTJ memory cells (hereinafter, alsosimply referred to as the “normal memory cells”) arranged in rows andcolumns, each of which cells can be accessed at random in accordancewith address signal ADD; and spare memory cells (not shown) forrepairing the normal memory cell suffering a defect (hereinafter, alsoreferred to as the “defective memory cell”).

Repair of a defective normal memory cell is performed by replacement ina unit of prescribed redundancy repair section. The spare memory cellsconstitute a plurality of redundant circuits (not shown) each forreplacement of a redundancy repair section including a defective memorycell. Generally, the unit of redundancy repair section is a memory cellrow, a memory cell column, or a data I/O line, in which cases, theredundant circuits each correspond to a spare row, a spare column, or aspare block corresponding to a spare I/O line, respectively. In thepresent embodiment, it is assumed that repair of a defective normalmemory cell is performed in a unit of memory cell column, as will bedescribed later in detail.

A plurality of write word lines WWL and read word lines RWL are arrangedcorresponding to the respective MTJ memory cell rows (hereinafter, alsosimply referred to as the “memory cell rows”). Bit lines BL and /BL arearranged corresponding to the respective MTJ memory cell columns(hereinafter, also simply referred to as the “memory cell columns”).

MRAM device 1 further includes a row decoder 20, a column decoder 25, aword line driver 30, and read/write control circuits 50, 60.

Row decoder 20 performs row selection in memory array 10 in accordancewith a row address RA indicated by address signal ADD. Column decoder 25performs column selection in memory array 10 in accordance with a columnaddress CA indicated by address signal ADD. Word line driver 30selectively activates read word line RWL or write word line WWL based onthe row selection result of row decoder 20. Row address RA and columnaddress CA indicate a memory cell that is selected as a target of dataread or data write (hereinafter, also referred to as the “selectedmemory cell”).

Write word line WWL is coupled to a prescribed voltage (typically, aground voltage) Vss in a region 40 on the other side of memory array 10from a region where word line driver 30 is arranged. Read/write controlcircuits 50, 60 collectively represent circuit groups arranged adjacentmemory array 10 for causing a data write current and a sense current(data read current) to pass through bit lines BL and /BL of a memorycell column corresponding to the selected memory cell (hereinafter, alsoreferred to as the “selected column”).

MRAM device 1 further includes a redundancy program circuit 100.Redundancy program circuit 100 includes a program element which can beblown with external laser irradiation. The program element is used tofixedly store a defective address corresponding to the column addressindicating the memory cell column (hereinafter, also referred to as the“defective column”) in which a defective memory cell exists. As will bedescribed later in detail, the program element according to the presentembodiment can be fabricated in parallel with the MTJ memory cells inthe step of forming the MTJ memory cells, without a need of dedicatedmanufacturing step.

Further, in a normal operation, redundancy program circuit 100 comparescolumn address CA with the stored defective address, to judge whether adefective column has been selected as a target of data read or datawrite.

In the case where a defective column has been selected by column addressCA, redundancy program circuit 100 designates an access to a redundantcircuit formed of spare memory cells, and also instructs column decoder25 to stop the access to the memory cell column indicated by columnaddress CA. Consequently, data read or data write is performed withrespect to the redundant circuit, instead of the memory cell columnindicated by column address CA.

In the case where column address CA does not correspond to a defectiveaddress, column decoder 25 performs a normal column select operation.Specifically, it selects the memory cell column indicated by columnaddress CA to perform data read or data write.

A redundant configuration in MRAM-device 1 is now described.

Referring to FIG. 2, memory array 10 includes normal memory cells MCarranged in n rows and m columns (n and m are natural numbers), and kredundant circuits RD1-RDk (k is a natural number). In the presentembodiment, the replacement/repair is performed in a unit of memory cellcolumn. Thus, each of redundant circuits RD1-RDk corresponds to a sparecolumn. Hereinafter, redundant circuits RD1-RDk are also collectivelyreferred to as redundant circuit RD.

When viewed as a whole, memory array 10 has the MTJ memory cells of theidentical configurations arranged in n memory cell rows and (m+k) memorycell columns.

Hereinafter, the memory cell columns formed of normal memory cells arealso referred to as the “normal memory cell columns”, and the memorycell columns formed of spare memory cells corresponding to respectiveredundant circuits RD1-RDk are also referred to as the “spare columns”.

Read word lines RWL1-RWLn and write word lines WWL1-WWLn are arrangedcorresponding to respective memory cell columns. Bit line pairsBLP1-BLPm are arranged corresponding to respective normal memory cellcolumns. Each bit line pair is formed of complementary bit lines. Forexample, bit line pair BLP1 is formed of bit lines BL1 and /BL1.

Spare bit line pairs SBLP1-SBLPk are arranged corresponding torespective spare memory cell columns. Each spare bit line pair is formedof complementary bit lines, as with the bit line pair. For example,spare bit line pair SBLP1 is formed of spare bit lines SBL1 and /SBL1.

Hereinafter, write word lines, read word lines, bit line pairs, bitlines, spare bit line pairs and spare bit lines will be collectivelyrepresented as WWL, RWL, BLP, BL (/BL), SBLP and SBL (/SBL),respectively. Specific write word line, read word line, bit line pair,bit line, spare bit line pair and spare bit line will be represented as,e.g., WWL1, RWL1, BLP1, BL1 (/BL1), SBLP1 and SBL1 (/SBL1), withaccompanying numerals.

The high voltage state (power supply voltages Vcc1, Vcc2) and lowvoltage state (ground voltage Vss) of data, signals and signal lineswill also be referred to as an “H level” and an “L level”, respectively.

The MTJ memory cells, i.e., normal memory cells MC and spare memorycells SMC, each have a tunneling magneto-resistance element TMR havingits resistance changed in accordance with a level of stored data, and anaccess transistor ATR serving as an access gate, connected in series.

Now, the configuration and data storage principle of the MTJ memory cellare described with reference to FIG. 3.

Referring to FIG. 3, tunneling magneto-resistance element TMR has aferromagnetic layer (hereinafter, also simply referred to as the “fixedmagnetic layer”) FL having a fixed, constant direction of magnetization,and a ferromagnetic layer (hereinafter, also simply referred to as the“free magnetic layer”) VL magnetized in a direction corresponding to anexternally applied magnetic field. A tunneling barrier (tunneling film)TB of an insulating film is provided between fixed magnetic layer FL andfree magnetic layer VL. Free magnetic layer VL is magnetized in adirection the same as or opposite to fixed magnetic layer FL inaccordance with the level of the stored data to be written. Fixedmagnetic layer FL, tunneling barrier TB and free magnetic layer VL forma magnetic tunnel junction.

The resistance of tunneling magneto-resistance element TMR changes inaccordance with a relative relation between the magnetization directionsof fixed magnetic layer FL and free magnetic layer VL. Specifically, theresistance of tunneling magneto-resistance element TMR becomes a minimalvalue Rmin when the magnetization directions of fixed magnetic layer FLand free magnetic layer VL are the same (parallel), while it becomes amaximal value Rmax when the two layers have opposite (anti-parallel)magnetization directions.

At the time of data write, read word line RWL is inactivated, and accesstransistor ATR is turned off. In this state, data write magnetic fieldsH (BL) and H (WWL) for magnetizing free magnetic layer VL are generatedby data write currents flowing through bit line BL and write word lineWWL, respectively. In particular, the data write current on bit line BLflows in a direction of either +Iw or −Iw, dependent on a level of writedata.

FIG. 4 is a conceptual diagram illustrating a relation between the datawrite current of the MTJ memory cell and the magnetization direction ofthe tunneling magneto-resistance element.

Referring to FIG. 4, the horizontal axis H (EA) represents a magneticfield being applied to free magnetic layer VL in tunnelingmagneto-resistance element TMR in an easy-to-magnetize axis (EA: EasyAxis) direction. The vertical axis H (HA) represents a magnetic fieldacting on free magnetic layer VL in a hard-to-magnetize axis (HA: HardAxis) direction. Magnetic fields H (EA) and H (HA) correspond to datawrite magnetic fields H (BL) and H (WWL), respectively, shown in FIG. 3.

In the MTJ memory cell, the fixed magnetization direction of fixedmagnetic layer FL is along the easy axis of free magnetic layer VL. Freemagnetic layer VL is magnetized along the easy axis direction, parallel(same) or anti-parallel (opposite) to the magnetization direction offixed magnetic layer FL, in accordance with the level of the storeddata. The MTJ memory cell can store data of one bit corresponding torespective one of the two magnetization directions of free magneticlayer VL.

The magnetization direction of free magnetic layer VL can be rewrittenonly in the case where a sum of applied magnetic fields H (EA) and H(HA) reaches a region outside the asteroid characteristic line shown inFIG. 4. In other words, the magnetization direction of free magneticlayer VL would not change when the data write magnetic fields appliedhave intensity that falls into the region inside the asteroidcharacteristic line.

As seen from the asteroid characteristic line, a magnetization thresholdvalue necessary to cause a change in magnetization direction of freemagnetic layer VL along the easy axis can be lowered by applying themagnetic field in the hard axis direction to free magnetic layer VL. Asshown in FIG. 4, the operating point at the time of data write isdesigned such that the stored data in the MTJ memory cell, i.e., themagnetization direction of tunneling magneto-resistance element TMR, canbe rewritten when prescribed data write currents are passed through bothwrite word line WWL and bit line BL.

With the operating point shown in FIG. 4 by way of example, in the MTJmemory cell as a target of data write, the data write magnetic field inthe easy axis direction is designed to have an intensity of H_(WR). Inother words, the value of the data write current to be passed throughbit line BL or write word line WWL is designed such that the relevantdata write magnetic field H_(WR) is obtained. In general, data writemagnetic field H_(WR) is expressed by a sum of a switching magneticfield H_(SW) necessary to switch the magnetization directions and amargin ΔH, i.e., H_(WR)=H_(SW)+ΔH.

The magnetization direction once written into tunnelingmagneto-resistance element TMR, i.e., the stored data in the MTJ memorycell, is held in a non-volatile manner until data is newly written.Although the resistance of each memory cell exactly corresponds to a sumof the resistance of tunneling magneto-resistance element TMR, an onresistance of access transistor ATR and other parasitic resistances, theresistance values other than that of tunneling magneto-resistanceelement TMR are constant irrelevant to stored data. Thus, hereinafter,the two kinds of resistances of a normal memory cell in accordance withstored data are also represented as Rmax and Rmin, and a differencetherebetween is represented as AR (i.e., ΔR=Rmax−Rim).

At the time of data read, the resistance level of a selected memorycell, or the stored data level, can be read by detecting, via bit lineBL, a current passing through tunneling magneto-resistance element TMRwhen access transistor ATR is turned on.

FIG. 5 is a cross sectional view showing a structure of the MTJ memorycell.

Referring to FIG. 5, the MTJ memory cell includes an access transistorATR formed on a semiconductor substrate SUB, and a conductive magneticfilm 105.

Access transistor ATR includes a source and a drain formed as impurityregions 110, 120 on semiconductor substrate SUB. Typically, a MOStransistor, which is a field effect transistor formed on a semiconductorsubstrate, is employed as access transistor ATR.

Impurity region 110 is connected to a ground voltage Vss, and serves asthe source. Impurity region 120 is electrically connected to conductivemagnetic film 105 via a metal interconnection 135 provided in a metalinterconnection layer M1 and a via contact 140 provided in a contacthole, and serves as the drain.

Read word line RWL is provided for control of a gate voltage of accesstransistor ATR, through which line it is unnecessary to pass a currentaggressively. Thus, from the standpoint of increasing the density, readword line RWL is formed with a polysilicon layer or a polycide structurein the same interconnection layer as a gate 130, without provision of anadditional, independent metal interconnection layer. By comparison,write word line WWL and bit line BL, through which the data writecurrents should be passed, are formed using metal interconnection layersM1 and M2, respectively.

Conductive magnetic film 105 has a stacked structure of a leadinterconnection 150, a tunneling magnetic layer 160 corresponding totunneling magneto-resistance element TMR, and a via contact 170. Leadinterconnection 150 is provided for electrically connecting tunnelingmagnetic layer 160 with via contact 140. Via contact 170 electricallyconnects tunneling magnetic layer 160 with bit line BL. Leadinterconnection 150 and via contact 170 are formed of metal films.

Referring to FIG. 6, tunneling, magnetic layer 160 includes: a NiFe filmand a Ta film provided as an underlayer 161; an antiferromagnetic layer162 formed of an IrMn film; magnetic layers 163 and 165 formed of CoFefilms; an insulating layer 164 (AlOx) sandwiched between magnetic layers163 and 165; a magnetic layer 166 formed of a NiFe film; and aprotective layer 167 formed of a Ta film.

Magnetic layer 163 corresponds to fixed magnetic layer FL in FIG. 3,while magnetic layers 165, 166 correspond to free magnetic layer VL inFIG. 3. Insulating layer 164 corresponds to tunneling barrier TB in FIG.3. Typical thicknesses of the respective layers are shown in theparentheses in FIG. 6.

Referring again to FIG. 2, the configuration of the memory array isdescribed in detail.

Normal memory cells MC in every other row are connected to either one ofbit lines BL and /BL. For example, focusing on the normal memory cellsbelonging to the first memory cell column, the normal memory cell in thefirst row is coupled to bit line /BL1, and the normal memory cell in thesecond row is coupled to bit line BL1. Likewise, the normal memory cellsand the spare memory cells in the odd rows are connected to one bitlines /BL1-/BLm, while those in the even rows are connected to the otherbit lines BL1-BLm. Similarly, spare memory cells SMC are connected tospare bit lines /SBL1-/SBLk in the odd rows, and connected to spare bitlines SBL1-SBLk in the even rows.

Memory array 10 further has a plurality of dummy memory cells DMC whichare coupled respectively to bit lines BL1, /BL1 to BLm, /BLm and sparebit lines SBL1, /SBL1 to SBLk, /SBLk.

Each dummy memory cell DMC has a dummy resistance element TMRd and adummy access element ATRd. A resistance sum Rd of dummy resistanceelement TMRd and dummy access element ATRd is set to an intermediatevalue of resistances Rmax and Rmin corresponding respectively to the Hlevel and the L level of data stored in MTJ memory cell MC, to satisfyRmax>Rd>Rmin. Dummy access element ATRd is typically formed of a fieldeffect transistor, as with the access element of the MTJ memory cell.Thus, hereinafter, the dummy access element is also referred to as thedummy access transistor ATRd.

Dummy memory cells DMC are arranged in two rows×(m+k) columns, tocorrespond to either one of dummy read word lines DRWL1 and DRWL2. Thedummy memory cells corresponding to dummy read word lines DRWL1 arecoupled respectively to bit lines BL1-BLm and spare bit lines SBL1-SBLk.The remaining dummy memory cells corresponding to dummy read word lineDRWL2 are coupled respectively to bit lines /BL1-/BLm and spare bitlines /SBL1-/SBLk. Hereinafter, dummy read word lines DRWL1 and DRWL2are also collectively referred to as dummy read word line DRWL.

Further, dummy write word lines DWWL1, DWWL2 are arranged correspondingto respective dummy memory cell rows. Although the arrangement of thedummy write word lines may be unnecessary for dummy resistance elementTMRd of a certain structure, dummy write word lines DWWL1, DWWL2designed in the same manner as write word line WWL are preferablyprovided to guarantee continuity in shape on the memory array and toavoid complexity of the manufacturing process.

At the time of data read, word line driver 30 selectively activates readword lines RWL and dummy read word lines DRWL1, DRWL2 to an H level (ofpower supply voltage Vcc1) in accordance with the row selection result.Specifically, when an odd row is selected and the normal memory cellsand the spare memory cells in the selected row are connected to bitlines /BL1-/BLm and spare bit lines /SBL1-/SBLk, then dummy read wordline DRWL1 is also activated, and the dummy memory cells are connectedto bit lines BL1-BLm and spare bit lines SBL1-SBLk. By comparison, whenan even row is selected, dummy read word line DRWL2 is activated inaddition to the read word line of the selected row.

At the time of data write, word line driver 30 couples an end of writeword line WWL of the selected row to power supply voltage Vcc2. Thispermits a data write current Ip in the row direction to flow on writeword line WWL of the selected row, from word line driver 30 towardregion 40. The write word lines of non-selected rows are coupled toground voltage Vss by word line driver 30.

Column select lines CSL1-CSLm for performing column selection areprovided corresponding to respective memory cell columns. Column decoder25 activates one of column select lines CSL1-CSLm to a selected state(of an H level) at each time of data write and data read, in accordancewith a decoded result of column address CA, i.e., the column selectionresult.

Further, spare column select lines SCSL1-SCSLk are providedcorresponding to respective spare memory cell columns. Spare columndrivers SCV1-SCVk, in response to spare enable signals SE1-SEk fromredundancy program circuit 100, activate corresponding spare columnselect lines to a selected state (of an H level). Generation of spareenable signals SE1-SEk will be described later in detail.

Still further, a data bus pair DBP is arranged for transmitting readdata and write data. Data bus pair includes complementary data buses DBand /DB.

Read/write control circuit 50 includes a data write circuit 51W, a dataread circuit 51R, column select gates CSG1-CSGm provided correspondingto respective memory cell columns, and spare column select gatesSCSG1-SCSGk provided corresponding to respective spare memory cellcolumns.

Hereinafter, column select lines CSL1-CSLm, spare column select linesSCSL1-SCSLk, column select gates CSG1-CSGm, and spare column selectgates SCSG1-SCSGk are also collectively referred to as column selectline CSL, spare column select line SCSL, column select gate CSG, andspare column select gate SCSG, respectively.

Each column select gate CSG has a transistor switch electrically coupledbetween data bus DB and corresponding bit line BL, and a transistorswitch electrically coupled between data bus /DB and corresponding bitline /BL. The transistor switches turn on/off in accordance with avoltage of corresponding column select line CSL. That is, each columnselect gate CSG, when corresponding column select line CSL is activatedto a selected state (of an H level), electrically connects data buses DBand /DB with corresponding bit lines BL and /BL, respectively.

Each spare column select gate SCSG has the same configuration as columnselect gate CSG. It electrically connects corresponding spare bit linesSBL and /SBL with data buses DB and /DB when corresponding spare columnselect line SCSL is activated to a selected state (of an H level).

Read/write control circuit 60 has short-circuit switch transistors 62-1to 62-m, 62-s 1 to 62-sk, and control gates 66-1 to 66-m and 66-s 1 to66-sk, provided corresponding to respective memory cell columns.Read/write control circuit 60 further has precharge transistors 64-1 a,64-1 b to 64-ma, 64-mb and 64-s 1 a, 64-s 1 b to 64-ska, 64-skb, whichare provided between bit lines BL1, /BL1 to BLm, /BLm and spare bitlines SBL1, /SBL1 to SBLk, /SBLk and ground voltage Vss, respectively.

Hereinafter, short-circuit switch transistors 62-1 to 62-m, 62-s 1 to62-sk, precharge transistors 64-1 a, 64-1 b to 64-ma, 64-mb and 64-s 1a, 64 -s1 b to 64-ska, 64-skb, and control gates 66-1 to 66-m and 66-s 1to 66-sk are also collectively referred to as short-circuit switchtransistor 62, precharge transistor 64 and control gate 66,respectively.

Each control gate 66 outputs an AND operation result betweencorresponding column select line CSL or spare column select line SCSLand a control signal WE. Thus, in the data write operation, the outputof control gate 66 is selectively activated to an H level in a selectedcolumn corresponding to column address CA or a spare column.

Short-circuit switch transistor 62 turns on/off in response to theoutput of corresponding control gate 66. Thus, in the data writeoperation, in a selected column corresponding to column address CA or aspare column, ends of bit lines BL and /BL or ends of spare bit linesSBL and /SBL are electrically connected to each other by short-circuitswitch transistor 62.

Each precharge transistor 64 turns on in response to activation of a bitline precharge signal BLPR, and precharges each of bit lines BL1, /BL1to BLm, /BLm and spare bit lines SBL1, /SBL to SBLk, /SBLk to groundvoltage Vss. Bit line precharge signal BLPR, generated by controlcircuit 5, is activated to an H level in an active period of MRAM device1, at least for a prescribed time period before execution of data read.By comparison, during the data read operation and the data writeoperation in the active period of MRAM device 1, bit line prechargesignal BLPR is inactivated to an L level, and precharge transistor 64 isturned off.

Now, the column select operation in MRAM device 1 is described. Asalready described above, the column select operation includes theredundancy control for the purpose of replacement/repair of a defectivecolumn.

Redundancy program circuit 100 includes a plurality of redundancycontrol units RPU(1)-RPU(k) provided corresponding to redundant circuits(spare columns) RD1-RDk, respectively. Redundancy control unitsRPU(1)-RPU(k) can store therein defective addresses FAD1-FADk,respectively. The i-th redundancy control unit RPU(i) determines whethercolumn address CA of h bits (h is a natural number) for indicating aselected column matches a programmed defective address FADi. Theconfigurations of redundancy control unit RPU(i) and of program elementsincluded therein will be described later in detail.

Redundancy control unit RPU(i) stores defective address FADi in a fixedmanner, and activates corresponding spare enable signal SEi to an Hlevel when the column address CA matches corresponding defective addressFADi. A normal enable signal NE is activated to an H level when columnaddress CA does not match any of defective addresses FAD1-FADk.

Column decoder 25, when normal enable signal NE is activated to an Hlevel, activates one column select line CSL corresponding to columnaddress CA. In response, an access to a normal memory cell is carriedout.

By comparison, when normal enable signal NE is inactivated to an Llevel, i.e., when column address CA matches any one defective addressFAD, column decoder 25 inactivates each of column select lines CSL1-CSLmcorresponding to the normal memory cells. On the other hand, one ofspare column select lines SCSL1-SCSLk is activated in response toactivation of any one of spare enable signals SE1-SEk. Thus, an accessto a spare memory cell, instead of the access to a normal memory cell,is carried out.

FIG. 7 shows operational waveforms during a data read operation and adata write operation, for illustrating replacement/repair in MRAM device1.

Firstly, the operation at the time of data write is described. Word linedriver 30, in accordance with a row selection result of row decoder 20,activates and connects write word line WWL corresponding to the selectedrow to power supply voltage Vcc2. Since an end of each write word lineWWL is coupled to ground voltage Vss in region 40, a data write currentIp is passed through write word line WWL of the selected row in adirection from word line driver 30 toward region 40. The data writecurrent is not passed through write word line WWL of a non-selected row,as it is maintained in an inactive state (L level: ground voltage Vss).

When column address CA does not match any of defective addressesFAD1-FADk, column select line CSL of the selected column correspondingto column address CA is activated to a selected state (of an H level),and one ends of bit lines BL and /BL of the selected column are coupledto data buses DB and /DB, respectively. Further, correspondingshort-circuit switch transistor 62 (FIG. 2) turns on, to short circuitthe other ends (opposite from the column select gate CSG side) of bitlines BL and /BL of the selected column.

When column address CA matches any one of defective addresses FAD1-FADk,corresponding spare column select line SCSL is activated to a selectedstate (of an H level), and one ends of corresponding spare bit lines SBLand /SBL, instead of bit lines BL and /BL of the selected column, arecoupled to data buses DB and /DB, respectively. Further, correspondingshort-circuit switch transistor 62 (FIG. 2) turns on, to short circuitthe other ends (opposite from the spare column select gate SCSG side) ofcorresponding spare bit lines SBL and /SBL.

Data write circuit 51W sets data buses DB and /DB to one and the otherof power supply voltage Vcc2 and ground voltage Vss. For example, whenwrite data DIN has a data level of L level, a data write current −Iw forwriting of L level data is passed through data bus DB. Data writecurrent −Iw is supplied to bit line BL of the selected column or tocorresponding spare bit line SBL, via column select gate CSG or sparecolumn select gate SCSG.

Data write current −Iw passed through bit line BL of the selected columnor corresponding spare bit line SBL is turned or folded back byshort-circuit switch transistor 62. Thus, a data write current +Iw inthe opposite direction is passed through the other bit line /BL or sparebit line /SBL. Data write current +Iw flowing through bit line /BL orspare bit line /SBL is transmitted to data bus /DB via column selectgate CSG or spare column select gate SCSG.

When write data DIN has a data level of H level, the data write currentsin the opposite directions can be passed through bit lines BL, /BL ofthe selected column or corresponding spare bit lines SBL, /SBL byreversing the voltage settings of data buses DB and /DB.

As such, when column address CA does not match any of defectiveaddresses FAD1-FADk, data write is performed on a normal memory cell(selected memory cell) having data write currents passed through bothcorresponding write word line WWL and bit line BL (/BL). By comparison,when column address CA matches any one defective address FAD, data writeis performed on a spare memory cell having data write currents passedthrough both corresponding write word line WWL and spare bit line SBL(/SBL).

At the time of data write, read word line RWL is maintained in anon-selected state (of an L level). Bit line precharge signal BLPR isactivated to an H level also at the time of data write, so that thevoltages of bit lines BL and /BL upon data write are set to groundvoltage Vss corresponding to the precharged voltage level at the time ofdata read. Thus, by matching the voltages of bit lines BL, /BLcorresponding to a non-selected column and of spare bit lines SBL, /SBLafter data write with the precharged voltage for data read, anadditional precharging operation before data read becomes unnecessary,so that the data read operation is accelerated.

Now, the data read-operation is described.

At the time of data read, word line driver 30 activates read word lineRWL corresponding to a selected row to an H level in accordance with therow selection result of row decoder 20. In a non-selected row, thevoltage level of read word line RWL is maintained in an inactive state(of an L level).

At the start of data read, read word line RWL of the selected row isactivated to an H level, and corresponding access transistors ATR turnon. The normal memory cells and the spare memory cells corresponding tothe selected row are electrically connected between bit line BL, /BL andspare bit line SBL, /SBL and ground voltage Vss, respectively, viaaccess transistors ATR.

Data read circuit 51R pulls up each of data buses DB and /DB with powersupply voltage Vcc1, and supplies a constant sense current Is.

Further, in accordance with column address CA, column select line CSL ofthe selected column or corresponding spare column select line SCSL isactivated to a selected state (of an H level), as in the case of datawrite.

When column address CA does not match any of defective addressesFAD1-FADk, sense current Is flows through tunneling magneto-resistanceelement TMR of the selected memory cell (normal memory cell) via databus DB (/DB) and bit line BL (/BL) of the selected column. Thus, avoltage change corresponding to the resistance (Rmax, Rmin) of theselected memory cell, or the stored data level, occurs in one of bitlines BL and /BL of the selected column and in one of data buses DB and/DB. Similarly, in the other of bit lines BL and /BL of the selectedcolumn and in the other of data buses DB and /DB, a voltage changecorresponding to the resistance Rd of dummy memory cell DMC occurs.

For example, in the case where the stored data level of the selectedmemory cell is “1” (resistance Rax), a voltage change AV1 occurs on oneof bit lines BL and /BL coupled to the selected memory cell that isgreater than a voltage change ΔVm occurring in the other of bit lines BLand /BL coupled to dummy memory cell DMC (ΔV1>ΔVm). Similarly, voltagechanges ΔVb1 and ΔVbm occur on data buses DB and /DB (ΔVbm>ΔVb1). Byusing data read circuit 51R to sense and amplify the voltage differencethus generated between data buses DB and /DB, the stored data in theselected memory cell can be output as read data DOUT.

On the other hand, when column address CA matches any of defectiveaddresses FAD1-FADk, sense current Is flows through a spare memory cellvia data bus DB (/DB) and spare bit line SBL (/SBL). Thus, a voltagechange corresponding to the resistance (Rmax, Rmin) of the spare memorycell, or the stored data level, occurs on one of spare bit lines SBL and/SBL and on one of data buses DB and /DB. A voltage change correspondingto resistance Rd of dummy memory cell DMC occurs on the other of sparebit lines SBL, /SBL and on the other of data buses DB, /DB, as in thecase where a normal memory cell is accessed.

As such, even if a defective column is selected by column address CA,data write and data read can be carried out without fault by accessing aspare memory cell of corresponding redundant circuit (spare column).Thus, it is possible to replace/repair a defective memory cell in a unitof memory cell column using a spare column corresponding to a redundantcircuit.

Further, the precharge voltages of bit lines BL, /BL and spare bit linesSBL, /SBL are set to ground voltage Vss. This prevents a dischargecurrent from flowing in a non-selected column from bit lines BL, /BL andspare bit lines SBL, /SBL via access transistors turned on in responseto activation of read word line RWL of a selected row. As a result,power consumption due to charge/discharge of the bit lines and the sparebit lines during the precharging operation can be reduced.

In addition, the voltage Vcc2 as the operating power supply voltage ofdata write circuit 51W is set higher than the voltage Vcc1 as theoperating power supply voltage of data read circuit 51R. This is becausethe data write currents Ip, ±Iw necessary to magnetize tunnelingmagneto-resistance element TMR of a selected memory cell at the time ofdata write is greater than the sense current Is necessary for data read.For example, if an external power supply voltage supplied from theoutside of MRAM device 1 is employed as power supply voltage Vcc2without converting, and this external power supply voltage is processedby a voltage down converter (not shown) to generate power supply voltageVcc1, then power supply voltages Vcc1 and Vcc2 can be suppliedefficiently.

Now, the configuration of the program element according to the firstembodiment is described in detail.

FIG. 8 is a circuit diagram showing the configuration of redundancycontrol unit RPU(i) shown in FIG. 2. Redundancy control unit RPU(i) isindicated as an application example of the program element according tothe first embodiment.

Referring to FIG. 8, redundancy control unit RPU(i) stores a defectiveaddress FADi of h bits with 2×h program elements 180 in a fixed manner,and performs matching between an input column address CA and defectiveaddress FADi. Column address CA is formed of address bits A1-Ah.

Redundancy control unit RPU has 2×h N-MOS transistors NT(1), /NT(1) toNT(h), /NT(h) electrically connected between a node N1 and a groundvoltage Vss via program elements 180. N-MOS transistor NT(1) has itsgate receiving input of address bit A1, and N-MOS transistor /NT(1) hasits gate receiving input of an inverted bit /A1 of address bit A1.Likewise, transistors NT(2)-NT(h) and /NT(2)-/NT(h) have their gatesreceiving inputs of address bits A2-Ah and their inverted bits /A2-/Ah,respectively.

Program elements 180 provided corresponding to respective address bitsA1-Ah and their inverted bits /A1-/Ah are selectively blown in responseto the respective bits of defective address FADi.

Redundancy control unit RPU(i) further has P-MOS transistors 201, 202connected in parallel with each other between a power supply voltageVcc1 and node N11 an inverter 204, and a signal driver 205. P-MOStransistor 201 has its gate receiving input of a precharge signal PC.Inverter 204 inverts the voltage level of node N1 and inputs the same toa gate of P-MOS transistor 202. Signal driver 205 generates a spareenable signal SEi in accordance with the voltage level of node N1.

Prior to each address input cycle of MRAM device 1, precharge signal PCis set to an L level and node N1 is precharged to power supply voltageVcc1. Once the address input cycle is started, precharge signal PC isset to an H level, and transistors 201 and 202 turn off, so that node N1is disconnected from power supply voltage Vcc1. In this state, inaccordance with an input address, address bits A1-Ah and their invertedbits /A1-/Ah are input to the gates of N-MOS transistors NT(1)-NT(h) and/NT(1)-/NT(h), respectively.

As a result, the voltage of node N1 is maintained at power supplyvoltage Vcc1 of the precharged level only in the case where the inputcolumn address CA and defective address FADi have their bits completelymatched with each other. In other cases, i.e., when the input addressand the defective address do not match, at least one current path isformed between node N1 and ground voltage Vss, and node N1 is pulleddown to ground voltage Vss.

Thus, spare enable signal SEi generated by signal driver 205 is set toan H level when defective address FADi and column address CA match witheach other, and otherwise set to an L level.

Now, examples of the structure of the program element according to thefirst embodiment are shown.

Referring to FIG. 9A, the program element 180 according to the firstembodiment has a magnetic layer 160#, provided at the same layer as andhaving the same structure as tunneling magnetic layer 160, electricallyconnected between a node 190 formed in a metal interconnection layer M2and a node 195 formed in a metal interconnection layer M1. One and theother of nodes 190 and 195 are electrically connected to ground voltageVss and a source of corresponding N-MOS transistor, as shown in FIG. 8.At least a portion of magnetic layer 160# constitutes a link portion 185that is designed to be fusible with external laser irradiation. That is,link portion 185 forms a so-called fuse.

An electrical contact between magnetic layer 160# and node 190 issecured by a via contact 170#, as in the case of the electrical contactbetween tunneling magnetic layer 160 and bit line BL (metalinterconnection layer M2) in the MTJ memory cell. Via contact 170# isprovided in the same layer as and with the same structure as via contact170 shown in FIG. 3.

Likewise, an electrical contact between node 195 and magnetic layer 160#is configured with a via contact 140# and a lead interconnection 150#,as in the case of the electrical contact between tunneling magneticlayer 160 and metal interconnection 135 (metal interconnection layer M1)in FIG. 3. Via contact 140# and lead interconnection 150# are providedin the same layers as and with the same structures as via contact 140and lead interconnection 150 shown in FIG. 3.

Referring to FIG. 9B, program element 180 may be formed of a metal layer150# formed in the same layer as lead interconnection 150 and a magneticlayer 160# formed in the same layer as and with the same structure astunneling magnetic layer 160. In this case, again, program element 180is designed such that a portion thereof constitutes a link portion 185which can be blown with external laser irradiation. The electricalcontacts between program element 180 and respective nodes 190 and 195are as shown in FIG. 9A, so that description thereof is not repeated.

Alternatively, program element 180 may be formed of a metal layer 150#formed in the same layer as lead interconnection 150, as shown in FIG.9C. In this case, again, it is configured such that a portion of programelement 180 constitutes a link portion 185 which can be blown withexternal laser irradiation. The electrical contacts between programelement 180 and respective nodes 190 and 195 are the same as in FIG. 9A,and thus, description thereof is not repeated.

As shown in FIGS. 9A-9C, the program element 180 according to thepresent embodiment is configured with at least one of metal layer 150#formed in the same layer as lead interconnection 150 in the MTJ memorycell and tunneling magnetic layer 160# formed in the same layer astunneling magnetic layer 160. Accordingly, it is possible to manufacturea program element which can fixedly store information by blowing withexternal laser irradiation, in parallel with the MTJ memory cells in themanufacturing step thereof, without provision of an additional,dedicated manufacturing step.

Metal layers 150, 150# shown in FIGS. 5 and 9A-9C each have a thicknesson the order of 300-1000 angstroms (1 angstrom=10⁻¹⁰ m). Thus,conditions suitable for laser blowing the multilayer film of metal layer150# and tunneling magnetic layer 160# will be, e.g., laserwavelength=0.5-1.5 μm, laser spot diameter=0.5-5 μm, and laser pulselength=5-30 ns. Any configuration from among FIGS. 9A-9C may be employeddepending on film or material of each magnetic layer, and in accordancewith the laser bowing conditions and the resistance value when the fuseis not blown.

Further, as in the structure examples in FIGS. 9A-9C, nodes 190 and 195to which program element 180 is connected may be arranged at upper andlower layers, respectively, of program element 180, to make theelectrical contacts between program element 180 and nodes 190, 195 thesame as the electrical contacts in the MTJ memory cell (FIG. 5). As aresult, peeling between the respective layers and others can beprevented, enabling stable manufacture of program element 180.

The program elements shown in FIGS. 10-10C are different from those inFIGS. 9A-9C in that both nodes 190 and 195 are arranged in an upperlayer of program element 180.

Correspondingly, the electrical contact structures between programelement 180 and respective nodes 190 and 195 are each secured by viacontact 170#, as in the case of the electrical contact between tunnelingmagnetic layer 160 and bit line BL (metal interconnection layer M2) inthe MTJ memory cell shown in FIG. 5. Via contact 170# is provided in thesame layer as and with the same structure as via contact 170 shown inFIG. 3.

With such a configuration, it is possible to arrange another signalinterconnection 197 or the like in a lower layer portion of programelement 180, i.e., in metal interconnection layer M1. Such efficientarrangement of signal interconnections results in reduction of chiparea.

The program elements shown in FIGS. 11A-11C differ from those in FIGS.9A-9C in that both nodes 190 and 195 are arranged in a lower layer ofprogram element 180.

Consequently, the electrical contact structures between program element180 and respective nodes 190 and 195 are each configured with viacontact 140# and lead interconnection 150#, as in the case of theelectrical contact between tunneling magnetic layer 160 and metalinterconnection 135 (metal interconnection layer M1) in FIG. 3. Viacontact 140# and lead interconnection 150# are provided in the samelayers as and with the same structures as via contact 140 and leadinterconnection 150, respectively, shown in FIG. 3.

With such a configuration, it is possible to arrange another signalinterconnection 197 or the like in the upper layer portion of programelement 180, i.e., in metal interconnection layer M2. As a result, chiparea can be reduced with such efficient arrangement of signalinterconnections.

As described above, the program element according to the firstembodiment of the present invention is configured as a fuse elementwhich utilizes the same structural portion as at least a portion of theconductive magnetic film constituting the MTJ memory cell. Thus, it canbe manufactured in parallel with the MTJ memory cells in themanufacturing step thereof, without a need to provide an additionalmanufacturing step dedicated to the program element (or fuse). As aresult, it is possible to build in a stable program element withoutincreasing the number of manufacturing steps of the MRAM device whichwould otherwise increase the manufacturing cost.

Second Embodiment

In the second embodiment, a configuration of a program circuit employingthe program element having the structure as described in the firstembodiment and capable of programming information before and after apackaging step is described.

FIG. 12 is a circuit diagram showing a configuration of a redundancycontrol unit RPU#(i) according to the second embodiment. The MRAM deviceaccording to the second embodiment is identical to that of the firstembodiment except for the configuration of each redundancy control unit.Thus, in the following, the configuration of the redundancy control unitof the second embodiment will be described in detail, while detaileddescription of the configurations and operations of the other portionswill not be repeated.

Referring to FIG. 12, the redundancy control unit RPU#(i) of the secondembodiment differs from redundancy control unit RPU(i) of the firstembodiment shown in FIG. 8 in that N-MOS transistors NPT(1), /NPT(1) toNPT(h), /NPT(h) are connected between node N1 and ground voltage Vss,instead of program elements 180. That is, in redundancy control unitRPU#(i), two N-MOS transistors connected in series are provided betweennode N1 and ground voltage Vss, corresponding to respective one ofaddress bits A1-Ah and respective one of their inverted bits /A1-/Ah.

N-MOS transistors NT(1)-NT(h) and /NT(1)-/NT(h) have their gatesreceiving inputs of address bits A1-Ah and their inverted bits /A1-/Ah,respectively, as in the case of redundancy control unit RPU(i) shown inFIG. 8. By comparison, N-MOS transistors NPT(1), /NPT(1) to NPT(h),/NPT(H) have their gates receiving inputs of program signals P(A1),P(/A1) to P(Ah), P(/Ah), respectively, which are generated by a programcircuit as will be described below.

FIG. 13 is a circuit diagram showing a configuration of the programcircuit according to the second embodiment.

In FIG. 13, the configuration of the j-th (j is an integer from 1 to h)program circuit PRC(j) from among h program circuits providedcorresponding to respective address bits A1-Ah is shown.

Referring to FIG. 13, program circuit PRC(j) has program elements 180 a,180 b, N-MOS transistors 211-214, a cross-coupled type amplifier 220, anN-MOS transistor 225 for supplying an operating current to cross-coupledtype amplifier 220, and current supply transistors 226 and 228 forsupplying read currents to program elements 180 a, 180 b.

Firstly, arrangement of program elements 180 a, 180 b is described.

FIG. 14 shows arrangement of the program elements in the program circuitshown in FIG. 13.

Program elements 180 a, 180 b are each formed to have the sameconfiguration as in the first embodiment and to include at leastmagnetic layer 160#. That is, they are each formed as shown in FIGS. 9A,9B, 10A, 10B, 11A, or 11B.

Referring to FIG. 14, program element 180 a has at least a magneticlayer 160# that is formed in the same layer as and with the samestructure as tunneling magnetic layer 160. An upper layer side ofmagnetic layer 160# of program element 180 a is electrically connectedto a node N(Aj). Node N(Aj) is connected via N-MOS transistor 211 to anode T1 which permits electrical contact from the outside afterpackaging. N-MOS transistor 211 has its gate receiving a control signalPRG.

A lower layer side of magnetic layer 160# constituting program element180 a is electrically connected to a ground node 210 such that tunnelingmagneto-resistance element TMR(Ai) is electrically connected betweennode N(Aj) and ground node 210.

As a result, a link portion 185 fusible with laser irradiation andtunneling magneto-resistance element TMR(Aj) are connected in seriesbetween node N(Aj) and ground node 210. The resistance of programelement 180 a, i.e., the resistance between node N(Aj) and ground node210, increases as link portion 185 is blown by laser irradiation.

When link portion 185 is not blown, the resistance of program element180 a corresponds to that of tunneling magneto-resistance elementTMR(Aj). Thus, application of an external voltage for giving a voltagestress sufficient to cause breakdown of the insulating film(corresponding to insulating film 164 in FIG. 4) in magnetic layer 160#to node T1 in response to activation of control signal PRG, enablesbreakdown of the relevant insulating film. The resistance of programelement 180 a is thus decreased from that before breakdown.

As such, in program element 180 a, the resistance increases with laserirradiation, and decreases with an external voltage input to node T1.Program element 180 b, configured in the same manner as program element180 a, has magnetic layer 160# with its upper layer side and lower layerside electrically connected to node N(/Aj) and ground node 210,respectively. Node N(/Aj) is connected via N-MOS transistor 212 to anode T2 which permits electrical contact from the outside afterpackaging. N-MOS transistor 212 has its gate receiving control signalPRG.

Referring again to FIG. 13, N-MOS transistors 211 and 212 are connectedbetween nodes T1, T2 and nodes N(Aj), N(/Aj), respectively, and havetheir gates each receiving control signal PRG, as described inconjunction with FIG. 14. N-MOS transistor 213 is electrically connectedbetween a node Ns at which a program signal P(Aj) is generated and nodeN(Aj). N-MOS transistor 214 is electrically connected between a node /Nsat which a program signal P(/Aj) is generated and node N(/Aj). N-MOStransistors 213 and 214 have their gates each receiving a control signalACT that is activated at the time of data read from the program circuit.

Cross-coupled type amplifier 220 has P-MOS transistors 221, 222 andN-MOS transistors 223, 224. P-MOS transistor 221 is electricallyconnected between power supply voltage Vcc1 and node Ns, and P-MOStransistor 212 is electrically connected between power supply voltageVcc1 and node /Ns. N-MOS transistor 223 is connected between node Ns anda drain of N-MOS transistor 225, and N-MOS transistor 224 is connectedbetween node /Ns and the drain of N-MOS transistor 225.

P-MOS transistor 221 and N-MOS transistor 223 have their gates eachelectrically connected to node /Ns, and P-MOS transistor 222 and N-MOStransistor 224 have their gates each electrically connected to node Ns.P-MOS transistor 226 is electrically connected between power supplyvoltage Vcc1 and node Ns, and P-MOS transistor 228 is electricallyconnected between power supply voltage Vcc1 and node /Ns. PMOStransistors 226 and 228 have their gates each receiving control signal/SA. N-MOS transistor 225 is electrically connected between sources ofN-MOS transistors 223, 224 and ground voltage Vss, and has its gatereceiving control signal SA.

Now, the operation of program circuit PRC#(j) is described.

At the time of programming to program circuit PRC#(j), laser irradiationor a voltage stress input for breakdown as described above is applied toeither one of program elements 180 a and 180 b. This causes a resistancedifference between node N(Aj) and ground node 210, and between nodeN(/Aj) and ground node 210.

In this state, when control signal SA is activated to an H level (/SA=Llevel) and control signal ACT is activated to an H level, there occurs avoltage difference between nodes Ns and /Ns corresponding to theabove-described resistance difference. This voltage difference isamplified by cross-coupled type amplifier 220 provided with an operatingcurrent from N-MOS transistor 225, so that complementary program signalsP(Aj) and P(/Aj) having levels corresponding to program inputs ofprogram elements 180 a and 180 b are generated at nodes Ns and /Ns.

Program signals P(A1), P(/A1) to P(Ah), P(/Ah) thus generated by theprogram circuits according to the second embodiment are input torespective gates of N-MOS transistors NPT(1), /NPT(1) to NPT(h), /NPT(h)shown in FIG. 12. This allows N-MOS transistors NPT(1), /NPT(1) toNPT(h), /NPT(h) to function in the same manner as respective programelements 180 in redundancy control unit RPU(i) of the first embodimentshown in FIG. 7. As a result, matching between a defective addressfixedly stored by a program input to program elements 180 a, 180 b andan input address (column address) becomes possible, as in the case ofredundancy control unit RPU(i) of the first embodiment.

As described in conjunction with FIGS. 13 and 14, each of programelements 180 a and 180 b has a resistance that increases when laser beamis input and decreases when a voltage stress is input, compared to thecase where there is no program input. Thus, in the program circuit shownin FIG. 13, one of program elements 180 a and 180 b may be configuredwith a reference resistance corresponding to a resistance inherent totunneling magneto-resistance element TMR, in which case, a programsignal can be generated in accordance with comparison of the resistancebetween node N(Aj) or N(/Aj) and ground node 210 with the referenceresistance. In other words, as shown in FIG. 13, two program elements180 a, 180 b complementarily receiving the program inputs may be used tostore program information of one bit. This improves reliability of theprogram information.

Now, a time period for applying the program input to the program circuitaccording to the second embodiment is described with reference to FIG.15.

Referring to FIG. 15, the MRAM device having undergone the wafer process(process P100) including manufacturing steps of a circuit element groupincluding MTJ memory cells, is subjected to a wafer test, and programinformation for use in redundancy repair of a defective memory celldetected in the wafer test is written into the program circuit (processP110). Programming in this step is carried out by laser irradiation.

The MRAM device is further subjected to a burn-in test in the waferstate (process P120) for accelerating manifestation of defects, andpackaged (process P130) after completion of the wafer burn-in test.

The MRAM device packaged is again subjected to the burn-in test in thepackaged state (process P140). The MRAM device having undergone theburn-in test after packaging is then subjected to a final operation test(process P150).

The defective memory cell finally detected in the process P150 isrepaired by redundancy repair conducted again (process P160). That is,the redundancy repair in this stage can be done by reprogramming withbreakdown of the program element. As a result, the state of the programelement is fixed with the irreversible physical breaking (process P170)by laser irradiation (process P110) or a voltage stress input (processP160) for causing breakdown. The MRAM device is shipped and mounted(process P180) after the programmed state is locked. Thus, stability ofthe program information improves compared to the case where programmingis done by magnetic data storage in an excessive MTJ memory cell.

As described above, according to the program circuit of the secondembodiment, information programming is possible before and after thepackaging step independently from each other, using the program elementthat can be manufactured without increasing the number of manufacturingsteps. That is, while the program input for repairing a defective memorycell detected in the wafer state after completion of the wafer processis carried out by laser irradiation, a defect occurring after therelevant step can also be repaired with redundancy replacement byprogramming the defective address with a voltage stress inputaccompanied by breakdown. As a result, defects detected at the wafertest, test after burn-in and test after packaging can be programmedaccumulatively for repair.

Third Embodiment

In the third embodiment, a configuration permitting program inputs in aplurality of steps using a program cell having the same structure as theMTJ memory cell, is described. The MRAM device of the third embodimentis identical to the MRAM device of the second embodiment except for theconfigurations of each program element and the program circuit. Thus, inthe following, the program element and the program circuit of the thirdembodiment will be described in detail, and detailed description of theconfigurations and operations of the other portions will not berepeated.

Referring to FIG. 16, the program element according to the thirdembodiment has the same structure as the MTJ memory cell shown in FIG.5. Thus, hereinafter, the program element of the third embodiment isalso referred to as the program cell.

The program cell includes an access transistor ATRp formed in the samemanner as access transistor ATR on a semiconductor substrate SUB, and aconductive magnetic film 105# including tunneling magneto-resistanceelement TMR.

Access transistor ATRp includes a source and a drain formed as impurityregions 110 p, 120 p on semiconductor substrate SUB. Impurity region 110p is connected to a ground node 210 (ground voltage Vss) and serves asthe source. Impurity region 120 is electrically connected to conductivemagnetic film 105# via a metal interconnection 135# provided in a metalinterconnection layer M1 and a via contact 140# provided in a contacthole, and serves as the drain.

A program word line PWL and a program bit line PBL are arranged in metalinterconnection layers M1 and M2, respectively, for carrying outmagnetic data writing to a program cell in the same manner as with theMTJ memory cell. Program word line PWL and program bit line PBLcorrespond respectively to write word line WWL and bit line BL shown inFIG. 5.

A gate 130 p receives a control signal /PRG that is set to an L level atthe time of magnetic writing of program data using program word line PWLand program bit line PBL, and set to an H level at the time of readingof the program data.

Conductive magnetic film 105# has the same structure as conductivemagnetic film 105 in the MTJ memory cell. Specifically, it has a leadinterconnection 150#, a tunneling magnetic layer 106# and a via contact170#, stacked one on another. Lead interconnection 150# is provided forelectrically connecting tunneling magnetic layer 160# with via contact140#. Via contact 170# electrically connects between tunneling magneticlayer 160# and program bit line PBL.

It is possible to perform, for the program cell of the third embodiment,both magnetic programming (data write) using program word line PWL andprogram bit line PBL, and programming with a blowing operation of a linkportion 185 formed of at least a portion of program bit line PBL.

That is, program bit line PBL has at least a portion designed to have ashape and structure fusible with external laser irradiation. Linkportion 185 may include a site other than program bit line PBL, e.g.,conductive magnetic film 105#.

Now, the configuration for magnetic writing to the program cell isdescribed with reference to FIGS. 17 and 18.

FIG. 17 is a conceptual diagram showing arrangement of program word linePWL and program bit line PBL with respect to the program cell.

Referring to FIG. 17, each program cell PMC is provided corresponding toa crossing point of program word line PWL and program bit line PBL whichare arranged along different directions. Currents (also referred to asthe “program currents”) for magnetically writing data to the programcell are passed through program word line PWL and program bit line PBL.Specifically, a program current Ip(P) for generating a magnetic fieldalong the hard axis (HA) direction in tunneling magneto-resistanceelement TMR within the program cell is passed through program word linePWL. A program current Iw(P) for generating a magnetic field along theeasy axis (EA) direction in the relevant tunneling magneto-resistanceelement TMR is passed through program bit line PBL.

Program word line PWL is arranged in the same direction with write wordline WWL arranged in memory array 10, while program bit line PBL isarranged along the same direction with bit line BL arranged in memoryarray 10. This makes the program cells and the MTJ memory cells in thememory array arranged in the same directions, so that manufacturing andmagnetizing steps thereof are simplified.

FIG. 18 is a circuit diagram showing a current supplying configurationat the time of data write to program cells.

Referring to FIG. 18, program cells PMCa, PMCb included in the sameprogram circuit have data of complementary levels written therein uponprogramming. One program word line PWL is arranged commonly for programcells PMCa, PMCb, and separate program bit lines PBL and /PBL arearranged corresponding to program cells PMCa and PMCb, respectively.Program word line PWL may further be shared by a plurality of programcircuits.

A program current supply portion 240 includes control gates 250, 252,260, 262 for controlling the directions of program currents ±Iw(P)supplied to program bit lines PBL, /PBL, voltage setting transistors254, 255, 264, 265 provided corresponding to program bit line PBL, andvoltage setting transistors 257, 258, 267, 268 provided corresponding toprogram bit line /PBL.

Control gate 250 outputs a NAND operation result between control signalPRG and program data PDj programmed in the j-th (j is an integer from 1to h) program unit. Control gate 252 outputs an AND operation resultbetween control signal PRG and inverted program data /PDj. Control gate260 outputs a NAND operation result between control signal PRG andinverted program data /PDj. Control gate 262 outputs an AND operationresult between control signal PRG and program data PDj.

Thus, when control signal PRG is at an L level, control gates 250, 260being the NAND gates have their outputs each fixed to an H level, andcontrol gates 252, 262 being the AND gates have their outputs each fixedto an L level. On the other hand, when control signal PRG is at an Hlevel, control gates 250, 252, 260, 262 have their outputs each set toan H level or an L level in accordance with program data PDj.

Voltage setting transistor 254, formed of a P-MOS transistor, iselectrically connected between one end of program bit line PBL and powersupply voltage Vcc2. Voltage setting transistor 255, formed of an N-MOStransistor, is electrically connected between the one end of program bitline PBL and ground voltage Vss.

Voltage setting transistor 264, a P-MOS transistor, is electricallyconnected between the other end of program bit line PBL and power supplyvoltage Vcc2. Voltage setting transistor 265, an N-MOS transistor, iselectrically connected between the other end of program bit line PBL andground voltage Vss.

Voltage setting transistors 257 and 258 are provided at an end ofprogram bit line /PBL in the same manner as voltage setting transistors254 and 255. Voltage setting transistors 267 and 268 are provided at theother end of program bit line /PBL in the same manner as voltage settingtransistors 264 and 265.

An output signal of control gate 250 is input to each gate of P-MOStransistors 254 and 267, and an output signal of control gate 252 isinput to each gate of N-MOS transistors 255 and 268. An output signal ofcontrol gate 260 is input to each gate of P-MOS transistors 257 and 264,and an output signal of control gate 262 is input to each gate of N-MOStransistors 258 and 265.

At the time other than program data writing (control signal PRG=Llevel), each voltage setting transistor is turned off, and program bitlines PBL and /PBL are electrically disconnected from power supplyvoltage Vcc2 and ground voltage Vss.

At the time of program data writing (control signal PRG=H level), onevoltage setting transistor is selectively turned on at each end of eachprogram bit line in accordance with the level of program data PDj, suchthat currents in the opposite directions flow through program bit linesPBL and /PBL.

For example, when program data PDj is at an H level, voltage settingtransistors 254 and 265 turn on and voltage setting transistors 255 and264 turn off with respect to program bit line PBL. For program bit line/PBL, voltage setting transistors 267 and 258 turn on, while voltagesetting transistors 257 and 268 turn off. Thus, program currents ±Iw(P)flow in the directions shown by solid line arrows in FIG. 18, acting onprogram cells PMCa and PMCb in the opposite directions.

When program data PDj is at an L level, on/off states of the respectivevoltage setting transistors are reversed. Thus, program currents ±Iw(P)flow through program bit lines PBL and /PBL in the directions shown bybroken line arrows in FIG. 18, which are opposite to those when PDj=Hlevel.

Program current ±Iw(P) generates a data write magnetic field along theeasy axis for magnetization of program cells PMCa, PMCb in the directionin accordance with program data PDj. Since the program currents flowthrough program bit lines PBL and /PBL in the opposite directionsirrelevant to the level of program data PDj, program cells PMCa and PMCbare magnetized along the easy axis in the opposite directions from eachother at the time of program data writing.

Program current supply portion 240 further includes a select transistor270 corresponding to program word line PWL. Select transistor 270 iselectrically connected between power supply voltage Vcc2 and an end ofprogram word line PWL, with its gate receiving an inverted signal /PRGof control signal PRG. The other end of program word line PWL is coupledto ground voltage Vss. Thus, at the time of program data writing,program current Ip(P) in a constant direction flows through program wordline PWL. Program current Ip(P) applies a program magnetic field in thehard axis direction to each program cell PMC.

Program data PDj is magnetically written into a program cell PMC appliedwith the magnetic fields along both the easy axis and the hard axis, aswith the MTJ memory cell in memory array 10.

Referring to FIG. 19, the program circuit according to the thirdembodiment differs from the program circuit of the second embodimentshown in FIG. 13 in that N-MOS transistors 211 and 212 for externallyapplying a voltage stress for breakdown are eliminated, and that programcells PMCa, PCMb are connected between nodes N(Aj), N(/Aj) and groundnode 210, respectively, instead of program elements 180 a, 180 b.

Program cells PMCa and PMCb are electrically connected to nodes N(Aj)and N(/Aj) by program bit lines PBL and /PBL, respectively. Otherwise,the configuration of the program circuit of the third embodiment isidentical to that of the program circuit shown in FIG. 13, so that thesame reference characters are employed and description thereof is notrepeated.

With such a configuration, prior to a blow input to a link portion 185including at least a portion of program bit line PBL, /PBL, data ofcomplementary levels can be magnetically written into program cells PMCaand PMCb to store program information of one bit in accordance with aresistance difference generated between nodes N(Aj), N(/Aj) and groundnode 210.

Further, after the magnetic programming, link portion 185 can be blownwith external laser irradiation, so that the resistance differencebetween program cells PMCa and PMCb can be fixed stably. The resistancedifference that occurs due to such programming with blowing isrelatively large compared to the resistance difference caused bymagnetic programming. Thus, it is possible to rewrite the magneticallywritten program information with the laser blow programming.

As described above, according to the configuration of the thirdembodiment, information programming is possible before and after thelaser blow independently from each other, using the program elementwhich can be manufactured without increasing the number of manufacturingsteps. As such, after information for repairing a defective memory celldetected in the wafer-state operation test (process P110 in FIG. 15) isprogrammed by magnetic writing, a test as to whether desired redundancyrepair is performed can be carried out without actual laser blow.Further, the confirmed program information can be stored stably with thelaser blow.

In the program circuit shown in FIG. 19, as in the second embodiment,one of program cells PMCa, PMCb may be formed with a referenceresistance, in which case, the program signal can be generated inaccordance with comparison of the resistance between node N(Aj) orN(/Aj) and ground node 210 with the reference resistance.

In the first through third embodiments, the case where a column addresscorresponding to a defective cell is programmed as a defective addressand redundancy repair is carried out in a unit of memory cell column hasbeen described. The present invention, however, may also be applicableto the case where redundancy repair is conducted in a unit of memorycell row or data I/O line. In such a case, an address indicating amemory cell row or a data I/O line corresponding to the defective cellmay be stored using the program element or the program circuit accordingto the embodiment of the present invention.

Further, in the first through third embodiments, the case where thedefective address for use in redundancy repair of a defective memorycell is stored by the program element and the program circuit of thepresent invention has been described. The present invention, however, isnot limited thereto. The program element and the program circuitaccording to the present invention are also applicable to the case ofprogramming any other information for tuning internal voltages, elementresistance values and others.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

1-10. (canceled)
 11. A semiconductor device comprising: a plurality ofmagnetic memory cells permitting random accesses; and a program circuitstoring information in a fixed manner; wherein each of said plurality ofmagnetic memory cells includes a tunneling magneto-resistance elementformed of a plurality of layers including a conductive magnetic film andan insulating film and having a resistance changed in accordance withmagnetically written data, said program circuit includes a first programelement formed of said plurality of layers as with said tunnelingmagneto-resistance element, a first program interconnection electricallyconnected to said first program element and a first node, a firstcurrent driving portion for supplying said first program interconnectionwith a current for magnetically writing data to said first programelement, and an amplifier portion reading said information in accordancewith a resistance between said first and second nodes, an upper layerside and a lower layer side of said plurality of layers constitutingsaid first program element are electrically connected to one and theother of said first program interconnection and said second node, andsaid first program interconnection is shaped such that at least aportion of its portion electrically connected between said first programelement and said first node is fusible by a first external input. 12.The semiconductor device according to claim 11, wherein said firstexternal input includes external laser irradiation.
 13. Thesemiconductor device according to claim 11, wherein said program circuitfurther includes a second program element formed of said plurality oflayers as with said tunneling magneto-resistance element, a secondprogram interconnection electrically connected to said second programelement and a third node, and a second current driving portion forsupplying said second program interconnection with a current formagnetically writing data to said second program element, an upper layerside and a lower layer side of said plurality of layers constitutingsaid second program element are electrically connected to one and theother of said second program interconnection and said second node, saidsecond program interconnection is shaped such that at least a portion ofits portion electrically connected between said second program elementand said third node is fusible with a second external input, and saidamplifier portion reads said information in accordance with comparisonof the resistance between said first and second nodes with a resistancebetween said second and third nodes.
 14. The semiconductor deviceaccording to claim 13, wherein each of said first and second externalinputs includes external laser irradiation.